The present application relates to semiconductor device fabrication, and more particularly, to the fabrication of asymmetric vertical field effect transistors (FETs).
Field Effect Transistors (FETs) are essential components of all modern electronic products. In its basic form, a FET device includes a source, a drain, a channel region between the source and the drain, and a gate electrode over the channel region to regulate electron flow between the source and the drain. In a conventional symmetric planar FET structure, the source region and the drain region are symmetrically positioned with respect to the gate electrode. There is an intrinsic trade-off between source/drain series resistance and gate to source/drain capacitance in such a symmetric device configuration. Specifically, FET saturated currents are more sensitive to source resistance and less sensitive to drain resistance. That is, FET drive current improves more with reduced source resistance, than with reduced drain resistance. Additionally, circuit delay is more sensitive to gate to drain capacitance than gate to source capacitance. That is, due to the Miller effect, the gate to drain capacitance can impact circuit delay significantly more than gate to source capacitance.
An asymmetric FET structure with asymmetrically positioned source region and drain region that allows simultaneously reducing source resistance and gate to drain capacitance thus is desirable. However, this asymmetric device configuration is difficult to implement in conventional planar MOSFETs due to the self-aligned symmetric nature of the gate spacer that is employed to define the positons of the source region and the drain region. Vertical MOSFETs are attractive candidates for 5 nm node and beyond due to better density scaling. The vertical device structure would allow easy incorporation of source/drain asymmetry effects.